md1820 features ? non-inverting, four channel mosfet driver ? 6.0ns rise and fall time ? 2.0a peak output source/sink current ? 1.8 to 5.0v input cmos compatible ? 5.0 to 10v total supply voltage ? smart logic threshold ? low jitter design ? four matched channels ? drives two p- and two n-channel mosfets ? outputs can swing below ground ? low inductance quad fat no-lead package ? high performance, thermally-enhanced package applications ? medical ultrasound imaging ? piezoelectric transducer drivers ? non-destructive testing (ndt) ? pin diode driver ? ccd clock driver/buffer ? high speed leve l translator general description the supertex md1820 is a high speed, four channel mosfet driver designed to drive high voltage p- and n-channel mosfets for medical ultrasound applications and other applications requiring a high output current for a capacitive load. the high-speed input stage of the md1820 can operate from a 1.8 to 5.0v logic interface with an optimum operating input signal range of 1.8 to 3.3v. an adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. the input logic levels may be ground-referenced, even though the driver is putting out bipolar signals. the level translator uses a proprietary circuit, which provides dc coupling together with high-speed operation. the output stage of the md1820 has separate power connections enabling the output signal l and h levels to be chosen independently from the supply voltages used for the majority of the circuit. as an example, the input logic levels may be 0 and 1.8v, the control logic may be powered by +5.0 and -5.0v, and the output l and h levels may be varied anywhere over the range of -5.0 to +5.0v. the output stage is capable of peak currents of up to 2.0a, depending on the supply voltages used and load capacitance present. the pe pin serves a dual purpose. first, its logic h level is used to compute the threshold voltage level for the channel input level translators. second, when pe is low, the outputs are hiz. this assists in properly precharging the ac coupling capacitors that may be used in series in the gate drive circuit of an external pmos and nmos transistor pair. typical application circuit high speed, four channel mosfet driver with non-inverting outputs outa outb outc outd +10v vdd vh +10v vss vl gnd ina inb inc ind pe supertex md1820 10nf 10nf +100v hv ou t -100v supertex tc6320 0.47f supertex tc6320 1.0f 1.0f -10v 1.0f +10v 1.0f 10 n f 10n f 3.3v cmos logic input s 0.47f supertex inc. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
2 md1820 v dd - v ss logic supply voltage 4.75 - 11.5 v 4.0v v dd 11.5v v ss low side supply voltage -5.5 - 0 v --- v h output high supply voltage v ss +2.0 - v dd v --- v l output low supply voltage v ss - v dd -4.0 v --- i ddq v dd quiescent current - 60 - a no input transitions, pe = 0 i hq v h quiescent current - 2.0 - a i ddq v dd quiescent current - 0.8 - ma no input transitions, pe = 1 i hq v h quiescent current - 2.0 - a i dd v dd average current - 3.5 - ma one channel on at 5.0mhz, no load i h v h average current - 10 - ma v ih input logic voltage high v pe -0.3 - v pe v for logic inputs ina, inb, inc, and ind v il input logic voltage low 0 - 0.3 v i ih input logic current high - 1.0 a i il input logic current low - - 1.0 a v ih pe input logic voltage high 1.70 3.30 5.25 v for logic input pe v il pe input logic voltage low 0 - 0.3 v r in_pe pe input impedance to gnd 100 - - k? dc electrical characteristics (v h = v dd = 10v, v l = v ss = gnd = 0v, v pe = 3.3v, t a = 25c) sym parameter min typ max units conditions absolute maximum ratings parameter value v dd -v ss , logic supply voltage -0.5v to +12.5v v h , output high supply voltage v l - 0.5v to v dd +0.5v v l , output low supply voltage v ss - 0.5v to v h +0.5v v ss , low side supply voltage -6.0v to +0.5v logic input levels v ss - 0.5v to gnd +5.5v maximum junction temperature +125c storage temperature -65c to 150c operating temperature -20c to +85c package power dissipation 2.2w thermal resistance ( ja )* 55c/w -g indicates package is rohs compliant (green) ordering information device 16-lead qfn 3.00x3.00mm body 1.00mm height (max) 0.50mm pitch md1820 MD1820K6-G 1820 ywll y = last digit of year sealed w = code for week sealed l = lot number = ?green? packaging product marking 16-lead qfn (k6) 1 16 16-lead qfn (k6) (top view) pin confguration absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. * 1.0oz 4-layer 3x4 pcb package may or may not include the following marks: si or supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
3 md1820 c in logic input capacitance - 5.0 10 pf --- r sink output sink resistance - 1.5 - ? i sink = 50ma r source output source resistance - 2.0 - ? i source = 50ma i sink peak output sink current - 2.0 - a --- i source peak output source current - 2.0 - a --- t irf input or pe rise & fall time - - 10 ns logic input edge speed requirement t plh propagation delay when output is from low to high - 6.5 - ns c load = 1000pf, see timing diagram input signal rise/fall time 2.0ns t phl propagation delay when output is from high to low - 6.5 - ns t r output rise time - 7.0 - ns t f output fall time - 7.0 - ns l t r - t f l rise and fall time matching - 1.0 - ns for each channel l t plh -t phl l propagation low to high and high to low matching - 1.0 - ns ?t dm propagation delay matching - 2.0 - ns device to device delay match t pe-on pe on-time - - 5.0 s v pe = 1.7 ~ 5.25v v dd = 7.5 ~ 11.5v -20 ~ 85 o c t pe-off pe off-time - - 4.0 s logic truth table dc electrical characteristics (cont.) (v h = v dd = 10v, v l = v ss = gnd = 0v, v pe = 3.3v, t a = 25c) sym parameter min typ max units conditions ac electrical characteristics (v h = v dd = 10v, v l = v ss = gnd = 0v, v pe = 3.3v, t a = 25c) sym parameter min typ max units conditions logic inputs output pe in h l v l h h v h l x high z supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
4 md1820 pe ina inb outa outb vdd vh inc ind outc outd md1820 gnd vss vl inb outc outd gnd vh pe ina vl outb outa vdd vh inc ind sub vss vl vh vl vh vl md1820 vss vdd vss vdd vss vdd vss vdd vss vdd vss vdd vss vdd level shifter level shifter level shifter level shifter level shifter simplifed block diagram detailed block diagram supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
5 md1820 10nf 10nf 0.1 f 10nf su pertex tc6320 10nf to piezoelectri c transducer vss vdd vh vl pe in a gn d in b in c in d outa +10v outb outc outd 0.47 f 0.47 f su pe rt ex tc6320 + 100v 0.1 f -100v 10nf 10nf su pe rt ex tc2320 vss vddv h vl pe in a gnd in b in c in d outa +5.0 v 3.3v cmos logic inputs outb out c outd +5.0v 0.47 f 0.47 f -5.0v 0.47 f -5.0v 0.47 f supertex md18 20 +10v +100v 0.1 f +100v 0.1 f -100v 0.1 f -100v su pertex tc6320 su pertex md1820 3.3v cmos logic inputs 0.1 f to piezoelectric transducer to piezoelectri c transducer 2-channel +100v to -100v pulser single channel 100v to 0v pulser typical applications supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
6 md1820 application information for proper operation of the md1820, low inductance bypass capacitors should be used on the various supply pins. the gnd pin should be connected to the logic ground. the ina, inb, inc, ind, and pe pins should be connected to a logic source with a swing of gnd to pe, where pe is 1.8 to 5.0v. good trace practices should be followed corresponding to the desired operating speed. the internal circuitry of the md1820 is capable of operating up to 100mhz, with the primary speed limitation being the loading effects of the load capacitance. because of this speed and the high transient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible. unless the load speci?cally requires bipolar drive, the vss and vl pins should have low inductance feed-through connections directly to a ground plane. if these voltages are not zero, then they need bypass capacitors in a manner similar to the positive power supplies. the power connection vdd should have a ceramic bypass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the powerleads. the voltages of vh and vl decide the output signal levels. these two pins can draw fast transient currents of up to 2.0a, so they should be provided with an appropriate bypass capacitor located next to the chip pins. a ceramic capacitor of up to 1.0f may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. pay particular attention to minimizing trace lengths, current loop area and using suf?cient trace width to reduce inductance. surface mount components are highly recommended. since the output impedance of this driver is very low, in some cases it may be desirable to add a small series resistance in series with the output signal to obtain better waveform transitions at the load terminals. this will of course reduce the output voltage slew rate at the terminals of a capacitive load. pay particular attention that parasitic couplings are minimized from the output to the input signal terminals. the parasitic feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. since the input operates with signals down to 1.8v even small coupled voltages may cause problems. use of a solid ground plane and good power and signal layout practices will prevent this problem. be careful that a circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry. t iming diagram v th / v pe curve v pe v th 0 0.5 1.0 1.5 2.0 1.0 2.0 3.0 4.0 5.0 0 v pe /2 v th vs v pe 0v 3.3v in t plh 10% 90% 50 % 0v 10 v 50% out t phl t r 90% 10 % t f supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
7 md1820 pin # function description 1 inb logic input. 2 vdd high side supply voltage. 3 vss low side supply voltage. vss is also connected to the ic substrate. it is required to connect to the most negative potential of voltage supplies. 4 inc logic input. 5 ind 6 gnd logic input ground reference. 7 vl supply voltage for n-channel output stage. 8 outc output drivers 9 outd 10, 11 vh supply voltage for p-channel output stage. 12 outa output drivers 13 outb 14 vl supply voltage for n-channel output stage. 15 pe power enable logic input. when pe is high, sets the input logic threshold. when pe is low, all outputs are at default state (see truth table) and ic in standby mode. 16 ina logic input. substrate the ic substrate is internally connected to the thermal pad. thermal pad and vss must be connected externally. pin description md1820 delay vs te mperature md1820 t r & t f vs te mperature md1820 delay vs v dd md1820 t r & t f vs v dd de la y ti me (ns) t pl h t ph l te mperature ( o c) -50 0 50 125 9 8 7 6 5 4 3 ti me (ns) t r t f t emperature ( o c) -50 0 50 125 9 8 7 6 5 4 3 de la y ti me (ns) t pl h t ph l v dd vo ltage (v) 5 8 10 12 14 12 10 8 6 4 2 ti me (ns) t r t f v dd vo ltage (v) 5 8 10 12 14 12 10 8 6 4 2 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
8 (the package drawing(s) in this data sheet may not refect the most current specifcations. for the latest package outline information go to http://www.supertex.com/packaging.html .) md1820 16-lead qfn package outline (k6) 3.00x3.00mm body, 1.00mm height (max), 0.50mm pitch doc.# dsfp-md1820 c011612 notes: 1. a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator. 2. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. 3. the inner tip of the lead may be either rounded or square. symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.80 0.00 0.20 ref 0.18 2.85* 1.50 2.85* 1.50 0.50 bsc 0.20 ? 0.00 0 o nom 0.90 0.02 0.25 3.00 1.65 3.00 1.65 0.30 ? - - max 1.00 0.05 0.30 3.15* 1.80 3.15* 1.80 0.45 0.15 14 o jedec registration mo-220, variation veed-4, issue k, june 2006. * this dimension is not specifed in the jedec drawing. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc.#: dspd-16qfnk63x3p050, version a092909. seating plane to p v iew side v iew bottom v iew a a1 d e d2 e b e2 a3 l l1 vi ew b vi ew b 1 note 3 note 2 note 1 (index area d/2 x e/2) note 1 (index area d/2 x e/2) 16 1 16 supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?2012 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
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